1. Field of the Invention
The present invention relates generally to content addressable memory (CAM) devices, and more particularly to controlling bit lines, like those that provide data to and/or from CAM cells for subsequent comparison with compare data values.
2. Background Art
Content addressable memory (CAM) devices, sometimes referred to as “associative memories,” can receive a compare data value (sometimes referred to as a comparand or search key), and compare such a value against a number of stored data values. In most configurations, such an operation can match a compare data value against a very larger number of stored data values (e.g., thousands or millions), essentially simultaneously.
Such rapid compare functions have resulted CAM devices enjoying wide application in various packet processing hardware devices, such as routers and network switches, to name just two. In a typical packet processing operation, a device can receive a packet. The packet can include a “header” having various data fields that indicate how the packet should be processed. The hardware device can use a matching function, provided by a CAM device, to compare one or more header fields to stored data values that can indicate how the packet is to be processed.
Many CAM device configurations can include a number of CAM memory cells arranged in a logical fashion (e.g., rows, words, etc.) to store data values for comparison with a search key. Such CAM memory cells typically include a storage circuit for storing one or more bit values as well as a compare circuit, for comparing the stored data value(s) with corresponding portions of a received search key.